View AD8468WBKSZ-RL_7804201.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rail -to - rail, fast, low power 2.5 v to 5.5 v, single - supply ttl/cmos comparator ad8468 features fully specified rail to rail at v cc = 2.5 v to 5.5 v input common - mode voltage from ?0.2 v to v cc + 0.2 v low glitch cmos - /ttl - compatible output stage 40 ns propagation delay low power : 2 mw at 2.5 v shutdown pin power supply rejection > 6 0 db ?40 c to +125c operation qualified for automotive applications applications automotive applications high speed instrumentation clock and data signal restoration logic level shifting or translation high speed line receivers threshold detection peak and zero - crossing detectors high speed trigger circuitry pulse - width modulators current - /voltage - controlled oscillators functional block dia gram ad8468 noninverting input inverting input q output + ? s dn 08853-001 figure 1. general description th e ad8468 is a fast comparator fabricated on xfcb2 .0 , an an alog devices , inc. , proprietar y pro cess. th is comparator is exceptionally versatile and easy to use. f eatures include an input range from ? 0.2 v t o v cc + 0.2 v, low noise , ttl - /cmos - compatible output drivers, and shu t down input s. the device offer s 40 ns pr opagation delay s driving a 15 pf load with 10 mv overdrive on 5 00 a t ypical supply current. a flexible power supply scheme allows th e device to operate with a single 2.5 v positive supply with a ?0.2 v to + 2. 7 v input signal range and up to a 5.5 v posi tive supply with a ?0. 2 v to +5.7 v input signal range. the ttl - /cmos -c ompatible output stage is designed to drive u p to 1 5 pf w ith full rated timing specifications and to degrade in a graceful and linear fashion as additional capacitance is added. the input stage of the comparator offers robust protec - tion against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. the ad8468 is available in a tiny 6 -lead sc70 package with a single- ended output and a shutdown pin. rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 an alog devices, inc. all rights reserved.
ad8468 rev. 0 | page 2 of 12 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics ............................................................. 3 absolute maximum ratings ............................................................ 4 thermal resistance ...................................................................... 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 typical performance characteristics ............................................. 6 applications information .................................................................7 power/ground lay out and bypassing ........................................7 ttl - /cmos - compatible output stage ....................................7 optimizing performance ..............................................................7 comparator propagation delay dispersion ..............................7 crossover bias point .....................................................................8 minimum input slew rate requirement ...................................8 typical application circuits ............................................................9 outline dimensions ....................................................................... 10 ordering guide .......................................................................... 10 automotive products ................................................................. 10 revision history /10 revision 0: initial version
ad8468 rev. 0 | page 3 of 12 specifications electrical character istics v cc = 2 .5 v, t a = ?4 0c to +1 25c. t ypical values are t a = 25 c , unless othe rwise noted. table 1 . parameter symbol conditions min typ max unit dc input characteristics voltage range v p , v n v cc = 2.5 v to 5.5 v ?0.2 v cc + 0.2 v common - mode range v cc = 2.5 v to 5 .5 v ?0.2 v cc + 0.2 v differential voltage v cc = 2.5 v to 5.5 v v cc v offset voltage v os ?10 .0 3 + 10 .0 mv bias current i p , i n ?0.4 +0.4 a offset current ?1.0 +1.0 a capacitance c p , c n 1 pf resistance, differential mode ?0.5 v to v cc + 0.5 v 200 7000 k? resistance, common mode ?0.5 v to v cc + 0.5 v 100 4000 k? active gain a v 80 db common - mode rejection cmrr v cc = 2.5 v , v cm = ?0.2 v to + 2.7 v 45 db v cc = 5 .5 v 45 db shutdown pin characteristics 1 v ih comparator i s operating 2.0 v cc v v il shutdown guaranteed ?0.2 +0.4 +0.4 v i ih v ih = v cc ?6 +6 a sleep time t sd l cc < 100 a 300 ns wake - up time t h v pp = 10 mv, output valid 150 ns dc output characteristics output voltage high level v oh i oh = 0.8 ma v cc ? 0.4 v output voltage low level v ol i ol = 0.8 ma 0.4 v ac performance 2 rise time /fall time t r , t f 10% to 90%, v cc = 2.5 v 25 to 50 ns 10% to 90%, v cc = 5.5 v 45 to 75 ns propagation delay t pd v od = 10 mv, v cc = 2.5 v 30 to 50 ns v od = 5 0 mv, v cc = 5.5 v 35 to 60 ns propagation delay skew rising to falling transition v cc = 2.5 v 4.5 ns v cc = 5.5 v 8 ns overdrive dispersion 10 mv < v od < 125 mv 12 ns common - mode dispersion ?0.2 v < v cm < v cc + 0.2 v 1.5 ns power supply supply voltage range v cc 2.5 5.5 v positive supply current i vcc v cc = 2.5 v 550 800 a v cc = 5.5 v 80 0 1300 a power dissipation p d v cc = 2.5 v 1 .375 2.0 mw v cc = 5.5 v 4.95 7.15 mw power supply rejection ratio psrr v cc = 2.5 v to 5.5 v ? 50 db shutdown current i sd v cc = 2.5 v to 5.5 v 2 50 35 0 a 1 the output is in a high impedance mode when the device is in shutdown mode . note that t his feature should be used with care because the enable/ disable time is much longer than with a true tri state output. 2 v in = 100 mv square input at 1 mhz, v cm = 0 v, c l = 15 pf, v cci = 2.5 v, unless otherwise noted.
ad8468 rev. 0 | page 4 of 12 absolute maximum rat ings table 2. parameter rating supply voltages supply voltage (v cc to gnd) ? 0.5 v to +6.0 v input voltages input volta ge ? 0.5 v to v cc + 0.5 v differential input voltage (v cc + 0.5 v) maximum input/output current 50 ma shutdown control pin applied voltage ( s dn to gnd) ? 0.5 v to v cc + 0.5 v maximum input/output current 50 ma output current 50 ma temperature o perating temperature, ambient ?4 0c to +125c operating temperature, junction 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 3 . thermal resistance package type ja 1 unit 6- lead sc70 426 c/w 1 measurement in still air. esd caution
ad8468 rev. 0 | page 5 of 12 pin configuration and function descriptions ad8468 top view (not to scale) q 1 v cc 6 gnd 2 s dn 5 v p 3 v n 4 08853-002 figure 2 . pin configuration table 4 . pin function descriptions pin no. mnemonic description 1 q noninverting output. q is at logic high if the analog voltage at the no ninverting input, v p , is greater than the analog voltage at the inverting input, v n . 2 gnd ground. 3 v p noninverting analog input. 4 v n inverting analog input. 5 s dn shutdown. drive this pin low to shut down the device. 6 v cc v cc supply.
ad8468 rev. 0 | page 6 of 12 typical performance characte ristics v cc = 2.5 v, t a = 25c, unless otherwise noted. 3.53.02.52.01.51.00.5 0 ?0.5 ?1.0 v cm at v cc (2.5v) 5 4 3 2 1 0 ?1 ?2 ?3 ?4 ?5 i b (a) +125c ?40c +25c 08853-003 figure 3. input bia s current vs. input common - mode voltage 150 100 50 0 od (mv) 60 55 50 45 40 35 30 25 20 propagation delay (ns) v cc = 5.5v rise delay v cc = 5.5v fall delay v cc = 2.5v rise delay v cc = 2.5v fall delay 08853-004 figure 4. propagation delay vs. input overdrive at v cc = 2.5 v and 5.5 v 4.0 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 1.5 1.0 0.5 0 ?0.5 ?1.0 load current (ma) v out (v) sink source 08853-005 figure 5. load current vs. v oh /v ol 0.5 1.0 1.5 2.0 2.5 3.0 38.0 37.8 37.6 37.4 37.2 37.0 36.8 36.6 36.4 36.2 36.0 propagation delay (ns) v cm at v cc (2.5v) propagation delay rise propagation delay fall 08853-006 figure 6. pro pagation delay vs. input common - mode voltage q 0.5v/div 10ns/div 08853-007 figure 7. 1 mhz output voltage waveform , v cc = 2.5 v 1v/div 10ns/div q 08853-008 figure 8. 1 mhz output voltage waveform , v cc = 5.5 v
ad8468 rev. 0 | page 7 of 12 applications information power/ground layout and bypassing the ad8468 comparator is a high speed device. despite the low noise output stage, it is essential to use proper high speed design techniques to achieve the specified performance. because comparators are uncompensated amplifiers, feedback in any phase relationship is likely to cause oscillations or undesired hysteresis. of critical importance is the use of low impedance supply p lanes, particularly the output supply plane (v cc ) and the ground plane (gnd). individual supply planes are recommended as part of a multilayer board. providing the lowest inductance return path for switching currents ensures the best possible performance i n the target application. it is also important to adequately bypass the input and output supplies. a 0.1 f bypass capacitor should be place d as close as possible to the v cc supply pin. the capacitor should be connected to the gnd plane with redundant via s placed to provide a physically short return path for output currents flowing back from ground to the v cc pi n. hi gh frequency bypass capacitors should be carefully selected for minimum inductance and esr. parasitic layout inductance should also be strictl y controlled to maximize the effectiveness of the bypass at high frequencies. ttl - /cmos -c ompatible output stage specified propagation delay performance can be achieved only by keeping the capacitive load at or below the specified minimums. the output of t he ad8468 is designed to directly drive one s chottky ttl , three low power s chottky ttl loads , or the equivalent. for large fan out s , bus es, or transmission lines , use an appropriate buffer to maintain th e excellent speed and stability of the comparator . wit h the rated 1 5 pf load capacitance applied, more than half of the total device propagation delay is output stage slew time . b ecause of this, the total prop agation delay decrease s as v cc decreases, and instability in the power supply may appear as excess delay dispersion. d elay is measure d to the 50% point for whatever supply is in use ; th us , the fastest times are observed with the v cc supply at 2.5 v, and larger values are observed when driving loads that switch at other levels. overdrive and input slew ra te dispersions are not significantly affected by output loading and v cc variations. the ttl - /cmos - compatible output stage is shown in the simplified schematic diagram ( see figure 9 ). because of its inherent symmetry and generally good behavior, this output stage is readily adaptable for driving various filters and other unusual loads. output q2 q1 +in ?in output stage v logic gain stage a2 a1 a v 08853-009 figure 9 . simplified schematic diagram of the ttl - /cmos - compatible output stage optimizing performan ce as with any high sp eed comparator, proper design and layout techniques are essential for obtaining the specified perform ance. stray capacitance, inductance, common power and ground impedances, or other layout issues can severely limit performance and can often cause oscillat ion. the source impedance should be minimized as much as is practicable. high source impedance , in combination with the parasitic input capacitance of the comparator, causes an undesirable degradation in bandwidth at the input, thus degrading the overall r esponse. higher impedances encourage undesired coupling. comparator propagati on delay dispersion the ad8468 comparator is designed to reduce propagation delay dispersion over a wide input overdrive range of 10 mv to v cc C 1 v. propagation delay dispersion is the variation in propagation delay that results from a change in the degree of overdrive or slew rate (how far or how fast the input signal exceeds the switching threshold). see figure 10 and figure 11. propagation delay dispersion is a specification that becomes important in high speed , time - critical applications , such as data communication, automatic test and measurement, and instru - mentation. it is also important in event - driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. ad8468 overdrive dispersion is typically < 12 ns a s the overdrive varies from 10 mv to 125 mv . this specification applies to both positive and negative signals because the device has very closely matched d elays for both positive -going and negative - going inputs and very low output skews. remember to add the actual device offset to the overdrive for repeatable dispersion measurements .
ad8468 rev. 0 | page 8 of 12 q output input voltage 500mv overdrive 10mv overdrive dispersion v n v os 08853-010 figure 10 . propagation delay o verdrive dispersion q output input voltage 10v/ns 1v/ns dispersion v n v os 08853-011 figure 11 . propagation delay slew rate dispersion crossover bias point rail - to - rail inputs of this type, i n both op amps and comparators , have a dual front - end design. certain devices are active near the v cc rail and others are active near the v ee rail or ground . at some predeter mined point in the common - mode range , a crossover occurs. at this point, norma lly v cc /2, the direction of the bias current reverse s, and the re are changes in measured offset voltages and currents. the ad8468 slightly elaborate s on this sche me. crossover points can be found at approximately 0.8 v and 1.6 v. minimum input slew r ate requirement with the rated load capacitance and normal good pc b oard design practice , as discussed in the optimizing performance section, th ese comparators should be stable at any input slew rate with no hysteresis. broadband noise from the input stage is observed in place of the violent chattering seen with most other high speed com parator s. with additional capacitive loading or poor bypassing , o scillation may be encountered . these oscilla - tion s are due to the high gain bandwidth of the comparator in combination with feedback through parasitics in the package and pc b oard. in many ap plications, chattering is not harmful.
ad8468 rev. 0 | page 9 of 12 typical application circuits ad8468 output 0.1f 2.5v to 5v 0.1f 2k ? 2k ? input 08853-012 figure 12 . self -b iased , 50% s licer ad8468 cmos v cc 2.5v to 5v 100 ? lvds output 08853-013 figure 13 . lvds -to- cmos r eceiver
ad8468 rev. 0 | page 10 of 12 outline dimensions 1.30 bsc compliant to jedec standards mo-203-ab 1.00 0.90 0.70 0.46 0.36 0.26 2.20 2.00 1.80 2.40 2.10 1.80 1.35 1.25 1.15 072809-a 0.10 max 1.10 0.80 0.40 0.10 0.22 0.08 3 12 4 6 5 0.65 bsc coplanarity 0.10 seating plane 0.30 0.15 figure 14. 6-lead thin shrink small outline transistor package (sc70) (ks-6) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding ad8468wbksz-r7 ?40c to +125c 6-lead thin shrink sm all outline transistor package (sc70) ks-6 y3f AD8468WBKSZ-RL ?40c to +125c 6-lead thin shrink sm all outline transistor package (sc70) ks-6 y3f 1 z = rohs compliant part. automotive products the ad8468wbksz models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that these automotive models may have specifications that differ from the commercial models; ther efore, designers should review the specifications section of this data sheet carefully. only the automotive grade products shown are a vailable for use in automotive applications. contact your local analog devices account representative for specific product ordering informat ion and to obtain the specific automotive reliability reports for these models.
ad8468 rev. 0 | page 11 of 12 notes
ad8468 rev. 0 | page 12 of 12 notes ? 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d0885 3-0- /10(0)

▲Up To Search▲

Price & Availability of AD8468WBKSZ-RL

	To Download AD8468WBKSZ-RL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .